NDLI: Improving the reliability of on-chip data caches under process variations

Content Provider	IEEE Xplore Digital Library
Author	Wei Wu Tan, S.X.-D. Jun Yang Shih-Lien Lu
Copyright Year	2007
Description	Author affiliation: Dept. of Comput. Sci., Univ. of Calif., Riverside, CA (Wei Wu)
Abstract	On-chip caches take a large portion of the chip area. They are much more vulnerable to parameter variation than smaller units. As leakage current becomes a significant component of the total power consumption, the leakage current variations induced thermal and reliability problem to the on-chip caches become an important design concern. This paper studies the impact of process variations, particular the leakage variations, on the temperature and reliability of on-chip caches. Our statistical simulation shows that, under process variation, 85% of the caches see shortened lifetime, with average lifetime being 81.6% of the ideal cache. At runtime, unevenly distributed dynamic power and the corresponding thermal variation would further deteriorate the situation. To mitigate this problem, we propose a dynamic cache subarray permutation scheme that can alleviate the thermal stress on a high-leakage area to improve the reliability of the caches. Experiments on 17 Spec2k benchmarks show that our scheme can extend the cache lifetime by up to 20.3%, and reduce the peak temperature by 7 degrees on average and more on data-intensive applications.
Starting Page	325
Ending Page	332
File Size	364386
Page Count	8
File Format	PDF
ISBN	9781424412570
ISSN	10636404
DOI	10.1109/ICCD.2007.4601920
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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