NDLI: A radix-10 SRT divider based on alternative BCD codings

Content Provider	IEEE Xplore Digital Library
Author	Vazquez, A. Antelo, E. Montuschi, P.
Copyright Year	2007
Description	Author affiliation: Dept. of Electron. & Comput. Sci., Univ. of Santiago de Compostela, Santiago de Compostela (Vazquez, A.; Antelo, E.)
Abstract	In this paper we present the algorithm and architecture a radix-10 floating-point divider based on an SRT non-restoring digit-by-digit algorithm. The algorithm uses conventional techniques developed to speed-up $radix-2^{k}$ division such as signed-digit (SD) redundant quotient and digit selection by constant comparison using a carry-save estimate of the partial remainder. To optimize area and latency for decimal, we include novel features such as the use of alternative BCD codings to represent decimal operands, estimates by truncation at any binary position inside a decimal digit, a single customized fast carry propagate decimal adder for partial remainder computation, initial odd multiple generation and final normalization with rounding, and register placement to exploit advanced high fanin mux-latch circuits. The rough area-delay estimations performed show that the proposed divider has a similar latency but less hardware complexity (1.3 area ratio) than a recently published high performance digit-by-digit implementation.
Starting Page	280
Ending Page	287
File Size	387936
Page Count	8
File Format	PDF
ISBN	9781424412570
ISSN	10636404
DOI	10.1109/ICCD.2007.4601914
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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