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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gunadi, E. Lipasti, M.H. |
| Copyright Year | 2007 |
| Description | Author affiliation: Electr. & Comput. Eng. Dept., Wisconsin Univ., Madison, WI (Gunadi, E.; Lipasti, M.H.) |
| Abstract | This paper presents the finished store buffer (or FSB), an alternative and position-insensitive approach for building a scalable store buffer for an out-of-order processor. Exploiting the fact that only a small portion of in-flight stores are done executing (i.e. finished) and waiting for retirement, we are able to build a much smaller and more scalable store buffer. Our study shows that we only need at most half of the number of entries in a conventional store queue if we buffer only the stores that have finished execution. Entries in the store buffer are allocated at issue and disallocated on retirement. A clever encoder circuit is used to provide positional searches without an explicitly positional queue structure. While reducing the access latency and power consumption significantly, our technique has virtually no detrimental effect on per-cycle performance (IPC). |
| Starting Page | 105 |
| Ending Page | 112 |
| File Size | 512006 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424412570 |
| ISSN | 10636404 |
| DOI | 10.1109/ICCD.2007.4601888 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-10-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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