NDLI: Broadband impedance matching for inductive interconnect in VLSI packages

Content Provider	IEEE Xplore Digital Library
Author	La Meres, B. Khairi, S.P.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA (La Meres, B.)
Abstract	Noise induced by impedance discontinuities from VLSI packaging is one of the leading challenges facing system level designers in the next decade. The performance of IC cores far exceeds that of current packaging technology. The risetimes of IC signals require that the interconnect of the package be treated as transmission lines. As a result, impedance discontinuities in the package cause reflections which may result in intermittent switching of digital signals and edge time degradation, both of which limit system performance. The major cause of the impedance discontinuity in the package is the high inductance of the wire bond interconnects. To compensate for this problem, capacitance can be placed near the wire bond to reduce its effective impedance over a given frequency range. This paper presents the application of this impedance matching technique for use in broadband digital signals that are prevalent in modern VLSI designs. Both static and dynamic compensation approaches are presented. The static compensator places pre-defined capacitances on the package and on the IC to surround the wire bond inductance. The dynamic compensator places a switchable capacitance on the IC that can be programmed to a desired value, thereby enabling the designer to overcome design and manufacturing variations in the Mire bond. Both techniques presented are shown to bound the reflections of the wire bond to less than 5% (down from 20% for an uncompensated structure) for wire bonds up to 5mm in length, and for frequencies up to 3GHz. In addition, both circuits utilizes less area than a typical wire bond pad, making them ideal for placement directly beneath the wire bond pads.
Sponsorship	IEEE Comput. Soc. Design Autom. Tech. Comm. (DATC) IEEE Circuits and Syst. Soc. Cadence Intel
Starting Page	683
Ending Page	688
File Size	418324
Page Count	6
File Format	PDF
ISBN	0769524516
DOI	10.1109/ICCD.2005.35
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Impedance matching Very large scale integration Bonding Wire Integrated circuit interconnections Transmission line discontinuities Integrated circuit packaging Capacitance Reflection Inductance
Content Type	Text
Resource Type	Article

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