NDLI: Temperature-dependent optimization of cache leakage power dissipation

Content Provider	IEEE Xplore Digital Library
Author	Peng Li Yangdong Deng Pileggi, L.T.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA (Peng Li)
Abstract	Leakage power consists of an increasing portion of the total power consumption for modern IC designs. Due to the strong inter-dependency between leakage and temperature, it becomes imperative to consider the thermal effects while optimizing the leakage power. In this paper, we present a temperature-dependent optimization methodology for on-chip caches. By integrating fast yet accurate coupled thermal-leakage simulations into an optimization flow, we are able to optimally tradeoff between the cache performance and leakage power while considering realistic on-chip temperature distribution. Our analysis indicates that for future memory intensive designs, the lack of chip temperature information can cause a significant error in the leakage power estimation, thus leading to non-optimal cache designs. Our results further imply that the optimization of cache performance and leakage power shall be attacked as part of the whole system design task in which chip-level floor planning and its thermal impacts are fully addressed.
Sponsorship	IEEE Comput. Soc. Design Autom. Tech. Comm. (DATC) IEEE Circuits and Syst. Soc. Cadence Intel
Starting Page	7
Ending Page	12
File Size	270970
Page Count	6
File Format	PDF
ISBN	0769524516
DOI	10.1109/ICCD.2005.104
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power dissipation Temperature Thermal management Energy consumption Design optimization Microprocessors Manufacturing Threshold voltage Circuits Optimization methods
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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