NDLI: Nonenumerative path delay fault coverage estimation with optimal algorithms

Content Provider	IEEE Xplore Digital Library
Author	Kagaris, D. Tragoudas, S. Karayiannis, D.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. Eng., Southern Illinois Univ., Carbondale, IL, USA (Kagaris, D.)
Abstract	A recent method proposed that a lower bound on the number of path delay faults excited by a given test set can be computed using a set independent lines that form a cut. For each line in the cut a subcircuit consisting of all paths that contain the line is defined, and a lower bound to the number of excited path delay faults can be obtained by working on the respective subcircuits. A polynomial time algorithm is presented here for computing the maximum cardinality set of independent circuit lines. Experimental results show that the more the subcircuits the better the lower bound on the number of excited path delay faults is. More subcircuits may be generated only in a heuristic manner. It was proposed to consider two or more line-disjoint cuts C/sub i/. We propose a technique where only one C/sub i/ must be a cut. This scheme is based on novel algorithms, and results in more subcircuits than the previous one.
Starting Page	366
Ending Page	371
File Size	752252
Page Count	6
File Format	PDF
ISBN	081868206X
ISSN	10636404
DOI	10.1109/ICCD.1997.628896
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay estimation Circuit faults Circuit testing Combinational circuits Polynomials Delay effects Robustness Electrical fault detection Fault detection Microwave integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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