NDLI: Power compiler: a gate-level power optimization and synthesis system

Content Provider	IEEE Xplore Digital Library
Author	Chen, B. Nedelchev, I.
Copyright Year	1997
Description	Author affiliation: Synopsys Inc., Mountain View, CA, USA (Chen, B.)
Abstract	Commercial synthesis tools traditionally perform timing and area optimization, however power reduction is rapidly becoming an equally important design goal. Recent research in power optimization has produced several algorithms, however, each algorithm is focused on one aspect of the whole power equation. This paper describes a commercial tool capable of optimizing power at the gate-level in addition to performing area and timing optimization. A power analysis engine that models all aspects of power consumption is integrated into the optimization tool so that all aspects of power are considered. Experimental results show an average 11.46% reduction on industrial circuits with a peak reduction of 66.62%. All delay constraints are met and an average 9.41% increase in area is observed.
Starting Page	74
Ending Page	79
File Size	659434
Page Count	6
File Format	PDF
ISBN	081868206X
ISSN	10636404
DOI	10.1109/ICCD.1997.628852
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Optimizing compilers Circuit synthesis Switching circuits Voltage Power dissipation Energy consumption Timing Capacitance Libraries Semiconductor device modeling
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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