NDLI: An efficient multi-way algorithm for balanced partitioning of VLSI circuits

Content Provider	IEEE Xplore Digital Library
Author	Tan, X. Tong, J. Tan, P. Park, N. Lombardi, F.
Copyright Year	1997
Description	Author affiliation: Dept. of Electron. Eng., Fudan Univ., Shanghai, China (Tan, X.)
Abstract	This paper presents an efficient algorithm for multi-way balanced partitioning of VLSI circuits. The proposed algorithm is still based on the widely used net-cut model, but its novelty is the potential gain function into the net-cut cost function to relax the single-cell-move constraint (as commonly encountered in the Kernighan-Lin algorithm) for balanced partitioning. This feature permits to move a group of cells (referred to as a Multi-Cell-Move strategy) for partitioning a circuit, while reducing its sensitivity to size constraint. The new multi-way partitioning algorithm is fully analyzed; expressions for the potential gain function (with respect to the multi-move operation) and the cost (for the min-cut objective function) are presented. The time complexity of the proposed partitioning algorithm is O(P/spl times/k/sup 2/ log/sub 2/ (k)), where k is the number of blocks and P is the number of pins. Simulation results are presented and a remarkable improvement is achieved compared with existing algorithms, such as the k-Dual Part algorithm.
Starting Page	608
Ending Page	613
File Size	1163813
Page Count	6
File Format	PDF
ISBN	081868206X
ISSN	10636404
DOI	10.1109/ICCD.1997.628928
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Partitioning algorithms Very large scale integration Circuits Cost function Algorithm design and analysis Pins
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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