NDLI: Post-layout circuit speed-up by event elimination

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Post-layout circuit speed-up by event elimination

Content Provider	IEEE Xplore Digital Library
Author	Vaishnav, H. Chi-Keung Lee Pedram, M.
Copyright Year	1997
Description	Author affiliation: Cadence Design Syst. Inc., San Jose, CA, USA (Vaishnav, H.)
Abstract	We propose a novel technique for post-layout delay optimization. This technique identifies the Boolean space corresponding to late arriving transitions at the outputs of delay-critical subcircuits within the given circuit. The transitions are eliminated from the outputs by implementing the corresponding logic separately and merging them with the original circuit through some control logic. Experimental results suggest that this technique can speed up circuits even when the circuits have already been optimized for delay to the fullest extent.
Starting Page	211
Ending Page	216
File Size	821215
Page Count	6
File Format	PDF
ISBN	081868206X
ISSN	10636404
DOI	10.1109/ICCD.1997.628870
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit synthesis Timing Integrated circuit interconnections Design optimization Logic Power dissipation Flexible printed circuits Iterative algorithms Delay estimation Contracts
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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