NDLI: Probabilistic analysis of Gallager B faulty decoder

Content Provider	IEEE Xplore Digital Library
Author	Yazdi, S.M.S.T. Hyungmin Cho Sun, Y. Mitra, S. Dolecek, L.
Copyright Year	2012
Description	Author affiliation: EE and CS Dept. Stanford (Mitra, S.) \|\| EE Dept. UCLA (Yazdi, S.M.S.T.; Sun, Y.; Dolecek, L.) \|\| EE Dept. Stanford (Hyungmin Cho)
Abstract	Today's mainstream electronic systems typically assume that transistors and interconnections operate correctly over their useful lifetime. For coming generations of silicon technologies, several causes of hardware failures, such as erratic bit errors, transient (soft) errors, and process variations, are becoming significant. In contrast to the traditional redundancy-based reliability solutions, the aim of a probabilistic design is to achieve high quality results and efficiency using erroneous or imperfect components along with a judicious allocation of resources. In this paper we focus on a probabilistic analysis of an LDPC Gallager B decoder made out of unreliable hardware components. Our analysis reveals the dependencies between the final BER at the output of the decoder and the errors in the components of the decoder. We demonstrate that a system design guided by our analysis can produce higher quality results compared to an arbitrary resource allocation. This resource allocation is of particular relevance to emerging storage applications that need to maintain extremely high levels of reliability even as the underlying technology scales deep into the nano-regime.
Starting Page	7019
Ending Page	7023
File Size	267322
Page Count	5
File Format	PDF
ISBN	9781457720529
ISSN	15503607
e-ISBN	9781457720536
e-ISBN	9781457720512
DOI	10.1109/ICC.2012.6364662
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-10
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Hardware Reliability Bit error rate Logic gates Iterative decoding
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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