NDLI: Performance model for mapping processing tasks to OpenFlow switch resources

Content Provider	IEEE Xplore Digital Library
Author	El Ferkouss, O.E. Ben Ali, R. Lemieux, Y. Omar, C.
Copyright Year	2012
Description	Author affiliation: Université du Québec à Montréal (UQAM) (El Ferkouss, O.E.; Omar, C.) \|\| Ericsson Research Canada (Ben Ali, R.; Lemieux, Y.)
Abstract	In a recent effort to push forward the powerful concept of software defined networks, OpenFlow has gained a lot of popularity as a practical approach to split the data and the control planes by standardizing an open interface that allow remote software controllers to dictate the forwarding behavior of network devices. The latest flexible version 1.1 of OpenFlow is limited to software forwarding plane implementations. In order to deliver high performance, we implement an OpenFlow v1.1 hardware forwarding plane based on network processors. Delivering the optimal performance requires finding the optimal mapping of OpenFlow tasks to hardware resources which is already known as an NP-hard combinatorial problem. In our work, we propose a performance model that helps choose a better mapping without the burden of implementing and comparing all possible mappings on network processor. Our model assumes that the performance bottleneck of the hardware forwarding pipeline comes from the lookup tasks. This is generally the case of OpenFlow lookup tasks based on more than 14 tuple headers and requiring high latency external memories in order to provide a large number of possible flow entries. Our model, validated using real hardware implementations comparisons, shows that the lookup tasks that use the same external memories in the same pipeline are not worth parallelizing. In fact, mapping them to different parallel processing elements will only increase the response time of the lookup memory which will slow down the forwarding pipeline.
Starting Page	1476
Ending Page	1481
File Size	223948
Page Count	6
File Format	PDF
ISBN	9781457720529
ISSN	15503607
e-ISBN	9781457720536
e-ISBN	9781457720512
DOI	10.1109/ICC.2012.6363651
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-10
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipeline processing Program processors Pipelines Hardware Memory management Multiprotocol label switching Load modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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