NDLI: Low power delay locked loop with all digital controlled SAR delay cell

Content Provider	IEEE Xplore Digital Library
Author	Ko-Chi Kuo Chung-Yuan Chang Si-Hsien Li
Copyright Year	2012
Description	Author affiliation: Dept. of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan (Ko-Chi Kuo; Chung-Yuan Chang; Si-Hsien Li)
Abstract	A delay-locked loop (DLL) with the successive approximation register (SAR) circuit is proposed to achieve fast locking effect. In order to lower the power consumption, a loop state controller (LSC) is proposed. When the loop is locked, the path which goes through the register is chosen to enter the sleeping mode, and disable part of the circuit in the power saving mode. When entering the sleeping mode, the register provides the fixed input code; the phase error comparator (PEC) keeps tracking process, voltage, temperature, and load (PVTL) variation. Once a variation is occurred, the PEC sends a signal to the loop state controller (LSC) and enables the circuit from the sleeping mode to tracking mode when the clock needs to be locked again. The proposed DLL only needs 6 cycles to lock again. The simulated locking range is from 150MHz to 900MHz in the TSMC 0.18µm process. The power consumptions are 15mW in locking mode and 9mW in sleeping modes.
Starting Page	120
Ending Page	123
File Size	510049
Page Count	4
File Format	PDF
e-ISBN	9781457717291
DOI	10.1109/APCCAS.2012.6418986
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-02
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Registers Synchronization Delay lines Logic gates Clocks Detectors
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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