NDLI: Cache utilization-aware scheduling for multicore processors

Content Provider	IEEE Xplore Digital Library
Author	Chu, E.T.-H. Wen-wei Lu
Copyright Year	2012
Description	Author affiliation: Department of Computer Science and Information Engineering, National Yunlin University of Science & Technology, Taiwan (Chu, E.T.-H.; Wen-wei Lu)
Abstract	A chip multiprocessor (CMP) consists of several cores which can execute tasks independently. Due to the budget and chip area limit, last level cache is usually shared among cores. If tasks running on different cores access the shared cache intensively and concurrently, it may lead to high cache miss rate and significant performance degradation. A commonly-used method is to co-schedule a task with good anti-interference ability and a task with poor anti-interference. However, if tasks have similar anti-interference abilities, it becomes difficult to generate a proper task assignment. In this paper, we identify two more indexes, intra-core cache contention and task interference ability, that primarily determine the utilization of shared cached. Based on the indexes, we develop a novel task scheduling, named cache utilization aware scheduling (CUAS), to reduce shared cache contention. CUAS first classifies tasks according to their anti-interference ability and interference ability. CUAS then distributes tasks to cores based on the effect of inter-core and intra-core cache contention. We conducted our experiments on an Intel Core2 Quad processor and adopted SPEC CPU2006 benchmark for evaluation. According to our experiment results, CUAS can significantly reduce shared cache contention and reduce total execution time at most 46% compared to existing methods.
Starting Page	368
Ending Page	371
File Size	551963
Page Count	4
File Format	PDF
e-ISBN	9781457717291
DOI	10.1109/APCCAS.2012.6419048
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-02
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Interference Multicore processing Processor scheduling Program processors Schedules Silicon Degradation High Performance Computing Multicore Cache Contention Task Scheduling
Content Type	Text
Resource Type	Article

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