NDLI: A modularized 3D heterogeneous system integration platform

Content Provider	IEEE Xplore Digital Library
Author	Chun-Ming Huang Chih-Chyau Yang Chien-Ming Wu Chih-Hsing Lin Chun-Chieh Chiu Yi-Jun Liu Chun-Chieh Chu Nien-Hsiang Chang Wen-Ching Chen
Copyright Year	2012
Description	Author affiliation: National Chip Implementation Center (CIC), Hsinchu, Taiwan (Chun-Ming Huang; Chih-Chyau Yang; Chien-Ming Wu; Chih-Hsing Lin; Chun-Chieh Chiu; Yi-Jun Liu; Chun-Chieh Chu; Nien-Hsiang Chang; Wen-Ching Chen)
Abstract	This paper proposes a modularized three-dimensional (3D) heterogeneous system integration platform architecture, namely, MorPACK (morphing package). The architecture of MorPACK platform achieves high performance and function flexibility with low silicon area cost by sharing the MorPACK common system platform (CSP) on heterogeneous system integration. An efficient reconfiguration is enabled thanks to the use of system bus interfaces and exchange the bare die/module by system dividing and tri-state interface connecting. Six SoC projects/designs are implemented to demonstrate the effectiveness of the proposed MorPACK platform. The average silicon area of each project is about 122.59 $mm^{2}$ using the TSMC 90 nm CMOS generic logic process technology. Compared with the total chip area 587.44 $mm^{2}$ obtained by implementing these projects separately, the results show that there are 79.13% fabrication cost reduced by the MorPACK platform. Besides, around 60% performance improvement of operation frequency can be benefited from the 3D-stacking technique.
Starting Page	396
Ending Page	399
File Size	795356
Page Count	4
File Format	PDF
e-ISBN	9781457717291
DOI	10.1109/APCCAS.2012.6419055
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-02
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Hardware IP networks Silicon Fabrication Computer architecture Central Processing Unit Platform-based Design 3D Heterogeneous Integrated Platform Mor-PACK
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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