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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Shastry, P.V.S. Agnihotri, A. Kachhwaha, D. Singh, J. Sutaone, M.S. |
| Copyright Year | 2011 |
| Description | Author affiliation: Department of Electronics and Telecommunication, MKSSS's Cummins College of Engineering for Women, Pune, INDIA (Shastry, P.V.S.; Agnihotri, A.; Kachhwaha, D.; Singh, J.) || Department of Electronics and Telecommunication, PIET's College of Engineering, Pune, INDIA (Sutaone, M.S.) |
| Abstract | This paper presents a combinational logic based Rijndael S-box implementation for the SubByte transformation on ASIC. Combinational implementation of S-box results in low cost, small area occupancy and high throughput as compared to the typical ROM based lookup table implementation with fixed and unbreakable access time. S-box has been implemented using 0.18µm CMOS standard cell library at 1.62V and runs at clock frequency of 71.43MHz. We could achieve throughput of 571.5Mbps with core utilization of 85%, core area occupied is $39.88.4µm^{2}$ using only 178 cells. Total power dissipation of the S-box implementation is 0.611mW which is quite lower than other literature available. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 765319 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781612848563 |
| ISSN | 15483746 |
| e-ISBN | 9781612848570 |
| e-ISBN | 9781612848556 |
| DOI | 10.1109/MWSCAS.2011.6026559 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-07 |
| Publisher Place | Korea (South) |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Three dimensional displays DVD US Department of Energy Encryption Composite Field Arithmetic AES ASIC S-Box |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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