NDLI: A 36-mW 320-MHz CMOS continuous-time sigma-delta modulator with 10-MHz bandwidth and 12-bit resolution

Content Provider	IEEE Xplore Digital Library
Author	Kuo-Che Hong Herming Chiueh
Copyright Year	2010
Description	Author affiliation: Institute of Communications Engineering, National Chiao Tung University, Hsin-Chu, Taiwan (Kuo-Che Hong; Herming Chiueh)
Abstract	A wide-bandwidth low-power CT ΔΣ modulator with 10MHz signal bandwidth is implemented in TSMC 0.18 µm CMOS process in this paper. To realize such application scenario, the proposed modulator comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time derivator structure. The simulation result achieves above 74-dB SNDR (12 ENOB) over a 10-MHz signal band. The power dissipation is 36mW from a 1.8-V supply and the energy per conversion is 235fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.
Starting Page	725
Ending Page	728
File Size	1004604
Page Count	4
File Format	PDF
ISBN	9781424477715
ISSN	15483746
e-ISBN	9781424477739
DOI	10.1109/MWSCAS.2010.5548717
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delta-sigma modulation Bandwidth Clocks Delay Circuit simulation Medical simulation Signal resolution Computed tomography Signal processing CMOS process
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in