NDLI: Pulse width variation tolerant clock tree using unbalanced cells for low power design

Content Provider	IEEE Xplore Digital Library
Author	Chawla, T. Marchal, S. Amara, A. Vladimirescu, A.
Copyright Year	2009
Description	Author affiliation: STMicroelectronics, 850, rue Jean Monnet, Crolles Cedex 38926, France (Chawla, T.; Marchal, S.) \|\| Institute Supérieur d'Electronique de Paris, 21 rue d'Assas, 75270 Cedex 06, France (Amara, A.; Vladimirescu, A.)
Abstract	Global and Environmental variations including Process (P), Voltage (V) and Temperature (T) constitute the biggest factor among all variations for any ASIC design. The age-old approach of using corners and margins to quantify the impact of variations is still applicable but the increasing margins limit the scaling of max achievable design frequency with technology, especially because of minimum pulse width violation. ASIC designs in current technology are working at these max clock frequencies. Moreover, as the importance of global N-to-P mismatch increases with technology, it increases the sensitivity of clock tree pulse-width to variations. Thus, to continue to scale the clock frequency in the future, we need to make margins and corners that are application specific. In this work, we have estimated the impact of PVT variations on the standard cells in a clock library using industrial models and spice simulations. We found that unbalancing the first stage with respect to the pulse edges in a cell reduced the variations by a factor of three without affecting the output behavior. We also found cells with opposite pulse-width variation characteristics enabling their combination in a path to minimize the overall variations.
Starting Page	443
Ending Page	446
File Size	926424
Page Count	4
File Format	PDF
ISBN	9781424444793
ISSN	15483746
DOI	10.1109/MWSCAS.2009.5236061
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-02
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Space vector pulse width modulation Clocks Frequency Application specific integrated circuits Delay Temperature Voltage Flip-flops Logic Libraries Pulse Width PVT variations Global N-to-P mismatch 45nm Clock Tree
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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