NDLI: A new charge redistribution D/A and A/D converter technique - pseudo C-2C ladder

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A new charge redistribution D/A and A/D converter technique - pseudo C-2C ladder

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A new charge redistribution D/A and A/D converter technique - pseudo C-2C ladder

Content Provider	IEEE Xplore Digital Library
Author	Lin Cong Black, W.C.
Copyright Year	2000
Description	Author affiliation: Iowa State Univ., Ames, IA, USA (Lin Cong)
Abstract	C-2C ladder-based DAC architecture is potentially very attractive because of its small area, high speed and low power consumption. However, the parasitic capacitances on the interconnecting nodes of C-2C ladder restrict the linearity of the DAC. In this paper, a pseudo C-2C ladder structure is proposed. It compensates for the parasitic effect by adjusting the capacitor values in the ladders according to an optimization algorithm with further adjustments possible via an adaptive calibration method. Using this technique, a 3.3 V 9.2 mW 12-bit 1.4 MSPS successive approximation ADC was implemented in an HP0.5 /spl mu/m single-poly triple-metal CMOS technology.
Starting Page	498
Ending Page	501
File Size	357562
Page Count	4
File Format	PDF
ISBN	0780364759
DOI	10.1109/MWSCAS.2000.951692
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-08-08
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Parasitic capacitance CMOS technology Linearity Mathematical model Energy consumption Semiconductor device modeling Voltage Optimization methods Approximation algorithms
Content Type	Text
Resource Type	Article

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