NDLI: Timing analysis of block replacement algorithms on disk caches

Content Provider	IEEE Xplore Digital Library
Author	Rajamoni, R. Bhagavathula, R. Pendse, R.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. Eng., Wichita State Univ., KS, USA (Rajamoni, R.)
Abstract	Cache memories are used to reduce the memory latency in systems. While instruction references of a CPU exhibit high temporal and spatial locality, disk references exhibit very minimal temporal and spatial locality. Owing to the fact that most of the block replacement algorithms exploit the available locality to improve cache performance, they are more effective with CPU instruction caches than with disk caches. This paper presents the results of an investigation of cache write policies and the impact of the Least Recently Used (LRU) and the Segmented LRU (SLRU) block replacement algorithms on the performance of disk caches. To obtain optimal performance at all workloads and cache sizes, an adaptive write caching policy is introduced. The adaptive write caching policy does a dynamic selection of the write policy at run time. Simulations reveal that when the cache size is less than 2 MB, caches employing adaptive write caching policy are 17% faster over caches employing write-back policy. For cache sizes of 16 MB and above the performance improvement is 9%. The performance improvement of caches employing adaptive write caching policy over caches employing write-through policy is 2.65% for cache sizes of 2 MB and is 27%, for cache sizes of 16 MB and above. The adaptive write caching policy yields optimum performance for many of the disk workloads and disk cache sizes.
Starting Page	408
Ending Page	411
File Size	377954
Page Count	4
File Format	PDF
ISBN	0780364759
DOI	10.1109/MWSCAS.2000.951670
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-08-08
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Algorithm design and analysis Hard disks Delay Writing Cache memory Random access memory Fabrication System performance Solid state circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in