NDLI: A fast, simple router for the Data-Intensive Architecture (DIVA) system

Content Provider	IEEE Xplore Digital Library
Author	Chang Woo Kang Draper, J.
Copyright Year	2000
Description	Author affiliation: Inf. Sci. Inst., Univ. of Southern California, Marina del Rey, CA, USA (Chang Woo Kang)
Abstract	This paper presents a fast, simple router design for implementing the Red Rover algorithm for a bidirectional ring. This design is very suitable for the Data-Intensive Architecture (DIVA) system, a system which demonstrates the benefits of embedded DRAM technology, because of its high performance as well as simple architecture and low cost. The key attributes of this router are one clock node-to-node latency, high channel throughput, and simple hardware implementation. The router architecture employs short-cut FIFO data paths, which makes the router speed independent of the channel buffer size (in terms of flits). A prototype implementation of the router achieves a maximum channel bandwidth of 5.12 Gb/s and runs at 80 MHz using 3.3 V CMOS signaling in 0.5 /spl mu/m technology. This high throughput and low latency were achieved without resorting to the use of complex high-speed signaling technologies.
Starting Page	188
Ending Page	192
File Size	525304
Page Count	5
File Format	PDF
ISBN	0780364759
DOI	10.1109/MWSCAS.2000.951617
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-08-08
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Throughput CMOS technology Algorithm design and analysis Random access memory Costs Clocks Hardware Prototypes Bandwidth
Content Type	Text
Resource Type	Article

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