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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chang Hoon Kim Soonhak Kwon Chun Pyo Hong In Gil Nam |
| Copyright Year | 2003 |
| Description | Author affiliation: Dept. of Comput. & Inf. Eng., Daegu Univ., Kyungbuk, South Korea (Chang Hoon Kim) |
| Abstract | In this paper, we propose a new bit-serial systolic array for computing division over GF(2/sup m/) using the standard basis representation. Based on a modified version of the binary extended GCD algorithm, we obtain a new data dependence graph (DG) and design an efficient bit-serial systolic array for division over GF(2/sup m/). Analysis shows that the proposed array provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic arrays with the same I/O format. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomials and has a unidirectional data flow and regularity, it is well suited for division circuits of elliptic curve cryptosystems (ECC). |
| Sponsorship | IEEE Circuits & Syst. Soc Mahanakorn Univ. Technol |
| File Size | 277696 |
| File Format | |
| ISBN | 0780377613 |
| DOI | 10.1109/ISCAS.2003.1205953 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-05-25 |
| Publisher Place | Thailand |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Systolic arrays Polynomials Computer architecture Elliptic curve cryptography Hardware Delay effects Circuits Gas insulated transmission lines Algorithm design and analysis Computational efficiency |
| Content Type | Text |
| Resource Type | Article |
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