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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Papaefstathiou, I. Leligou, H.-C. Orphanoudakis, T. Kornaros, G. Zervos, N. Konstantoulakis, G. |
| Copyright Year | 2003 |
| Description | Author affiliation: ICS-FORTH, Crete, Greece (Papaefstathiou, I.) |
| Abstract | In this paper, we describe the architecture of the scheduling components integrated in a novel programmable processor architecture. The paper explores the requirements for scheduling in the environment of a network processor, designed for efficient protocol processing in high-speed networking. We focus on the implementation of services with weighted priorities and shaping of traffic on the transmission path as a means to support QoS for real time applications. Taking into account that one of the main problems when designing hardware devices for network processing is the relatively low throughput and capacity of the memories (mainly off-chip) we describe design alternatives and analyze the performance vs. cost trade-offs. The architecture of a novel processor architecture developed by the Protocol Processor Project (PRO3) is described and is used as reference to explore the intricacies of the scheduler components and identify parameters that affect the components design and performance. |
| Sponsorship | IEEE Circuits & Syst. Soc Mahanakorn Univ. Technol |
| File Size | 372569 |
| File Format | |
| ISBN | 0780377613 |
| DOI | 10.1109/ISCAS.2003.1205899 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-05-25 |
| Publisher Place | Thailand |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Processor scheduling High-speed networks Hardware Computer architecture Throughput Transport protocols Telecommunications Application specific integrated circuits Reduced instruction set computing Process design |
| Content Type | Text |
| Resource Type | Article |
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