NDLI: A low-area, high-speed, processor array architecture for field ALU over GF $(2^{m})$

Content Provider	IEEE Xplore Digital Library
Author	Fayed, M. Watheq El-Kharashi, M. Gebali, F.
Copyright Year	2007
Description	Author affiliation: Univ. of Victoria, Victoria (Fayed, M.)
Abstract	We propose a novel, low-area, high-speed architecture for the basic operations over $GF(2^{m}).$ The proposed architecture is a processor array based, which utilizes the most significant bit multiplication algorithm and polynomial basis. A design space exploration to optimize the area and speed of the proposed architecture was done. We use the National Institute of Standard and Technology recommended polynomials, which makes our design secure and more suitable for cryptographic applications. The proposed architecture is implemented for misin {163,283,571} on a Xilinx XC2V4000 device to verify its functionality and measure its performance. We achieve a frequency of 264 MHz, which allows the architecture to calculate $GF(2^{163})$ multiplication in 640 ns and inversion in 14.357 mus.
Starting Page	297
Ending Page	305
File Size	243413
Page Count	9
File Format	PDF
ISBN	9781424414307
DOI	10.1109/ITICT.2007.4475666
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-16
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite or Galois Field $GF(2^{m})$ Inverters $GF(2^{m})$ Squaring $GF(2^{m})$ Multiplication Galois fields Delay Processor Array $GF(2^{m})$ Arithmetic Elliptic Curve Cryptography (ECC) $GF(2^{m})$ Inversion Computer architecture Elliptic curve cryptography Polynomials Hardware Space exploration Arithmetic Clocks
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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