NDLI: System-on-a-chip global interconnect optimization

Please wait, while we are loading the content...

15th Annual IEEE International ASIC/SOC Conference

Proceedings 15th Annual IEEE International ASIC/SOC Conference (Cat. No.02TH8626)

Architecture and implementation of an embedded reconfigurable logic core in CMOS 0.13 /spl mu/m

Any-size instruction abbreviation technique for embedded DSPs

Low-cost design and implementation of an ICA-based blind source separation algorithm

VLSI implementation of Ogg Vorbis decoder for embedded applications

Interactive broadcast radio architecture

An oldest-first selection logic implementation for non-compacting issue queues [microprocessor power reduction]

Predictive precharging for bitline leakage energy reduction [microprocessor caches]

Memory system compression and its benefits

Virtual in-circuit emulation for timing accurate system prototyping

An effective soft module floorplanning algorithm based on sequence pair

Using formal techniques for identifying uninitialized registers in SoC designs

XM-ADL, an extensible markup architecture description language

Realization of compact low-power ripple-flash A/D converter architectures using conventional digital CMOS technology

DAC nonlinearity effects in a wide-band sigma-delta modulator architecture

An 8-bit 200 MS/s CMOS folding/interpolating ADC with a reduced number of preamplifiers using an averaging technique

Design of transport triggered architecture processor for discrete cosine transform

A CMOS Miller hold capacitance sample-and-hold circuit to reduce charge sharing effect and clock feedthrough

Split accumulator with phase modulation for high speed low power direct digital synthesizers

Adaptive PRML SOC development for read/write capable optical drives

Power management of the autonomous error-tolerant cell

A new power modeling approach for transversal filters based on physically oriented design

An analytical power estimation model for crossbar interconnects

Highly efficient digital CMOS accelerator for image and graphics processing

Design of an integrated silicon connectionist retina

Influence of MPEG-4 parameters on system energy

Extending scaling theory by adequately considering velocity saturation

Fast system-level design space exploration for low power configurable multimedia systems-on-chip

SoC gate level design migration

Rapid system-level performance evaluation and optimization for application mapping onto SoC architectures

A 200/spl deg/C automatic gain controlled oscillator for MEMS resonator with an MRC transimpedance

A circuit technique for accurately measuring coupling capacitance

Clock feedthrough in CMOS analog transmission gate switches

Switched-current implementation of two-dimensional DCT for image processing

Power reduction via an MTCMOS implementation of MOS current mode logic

A low-voltage low-noise CMOS digital family

HyPipe: a new approach for high speed circuit design

On-chip interconnects for next generation system-on-chips

On-chip segmented bus: a self-timed approach [SOC]

Next generation CoreConnect/spl trade/ processor local bus architecture

Complementary substrate-triggered SCR devices for on-chip ESD protection circuits

ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins

A hierarchical block-based modeling methodology for SoC in GENESYS

Impact of technology scaling and packaging on dynamic voltage scaling techniques

A new low-power and area efficient RAKE receiver design without incurring performance degradation

A flexible, module-based SoC-approach for low-power VoIP-applications

Design of a shared buffer management scheme for ATM switches

Design and synthesis of direct connected network devices controller

Rapid design space exploration of DSP applications using programmable SoC devices-a case study

Development platform implementation and verification for UMTS UE MODEM

Design of broadband controller for residential gateway applications

Reducing dynamic power and leakage power for embedded systems

Experimental evaluation of a compiler-based cache energy optimization strategy

Instruction compression and encoding for low-power systems

Design of enhanced differential cascode voltage switch logic (EDCVSL) circuits for high fan-in gate

Variable threshold voltage keeper for contention reduction in dynamic circuits

Three phase domino logic circuit

Long-term power minimization of dual-V/sub T/ CMOS circuits

A low-power UHF RF frontend for a low-IF receiver

A spread spectrum based communication system for an integrated sensor microsystem

FPGA implementation of a sigma-delta (/spl Sigma/-/spl Delta/) architecture based digital I-F stage for software radio

High Q embedded inductors in silicon for RF applications

Analytical performance models for RLC interconnects and application to clock optimization

Linear timing analysis of SOC synchronous circuits with level-sensitive latches

Clock network analysis at the pre-layout stage for efficient clock tree synthesis [SOC design]

Scaled accumulation FETs for ultra-low power logic

A compact model for projections of future power supply distribution network requirements

Two orders of magnitude leakage power reduction of low voltage SRAMs by row-by-row dynamic V/sub dd/ control (RRDV) scheme

Low power bus encoding with crosstalk delay elimination [SoC]

Low-power, low-latency global interconnect

System-on-a-chip global interconnect optimization

Time delay, crosstalk and repeater insertion models for high performance SoC's

Design sensitivities to variability: extrapolations and assessments in nanometer VLSI

A new placement algorithm for an interconnect centric design flow

Variation of inductance with frequency in high performance power distribution grids [ICs]

Interconnect structures for high-speed long-distance signal transmission [LSI interconnects]

Characterizing dynamic and leakage power behavior in flip-flops

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

A minimal source-synchronous interface

System-level power evaluation of an embedded software data block processing algorithm

An interface protocol component modeling language

Quantifying the impact of current-sensing on interconnect delay trends

Yield assurance at 0.13 micron technology and below

Crystal oscillator parameter and design challenges

An introduction to bluetooth a standard for short range wireless networking

Advanced high-performance microprocessor design challenges and solutions

Low-voltage current-mode analog circuit structures and their applications

Workshop on transceiver architecture and components for wireless communication system

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)

Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)

System-on-a-chip global interconnect optimization

Content Provider	IEEE Xplore Digital Library
Author	Naeemi, A. Venkatesan, R. Meindl, J.D.
Copyright Year	2002
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Naeemi, A.; Venkatesan, R.; Meindl, J.D.)
Abstract	The width of global interconnects is optimized to have a large bisectional bandwidth along with a small latency, power dissipation, repeater area and via blockage. The optimal wire width, which maximizes the product of data flux density OD and reciprocal delay 1//spl tau/, is independent of the interconnect length and can be used for all global interconnects. Data flux density OD (per unit width) determines the bisectional bandwidth and therefore, the total number of bits per second that global interconnect levels can potentially transfer. Using optimal wire width decreases the latency, energy dissipation, and repeater area by 42%, 30%, and 84%, respectively compared to using half the optimal wire width at the price of 14% smaller bisectional bandwidth.
Starting Page	399
Ending Page	403
File Size	371623
Page Count	5
File Format	PDF
ISBN	0780374940
DOI	10.1109/ASIC.2002.1158092
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Delay Wire Repeaters Bandwidth Conductivity Clocks Frequency Capacitance Power system interconnection
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in