NDLI: Using formal techniques for identifying uninitialized registers in SoC designs

Content Provider	IEEE Xplore Digital Library
Author	Saha, A. Ranmale, R.S.
Copyright Year	2002
Description	Author affiliation: Broadband Silicon Technol. Center, Texas Instruments, Bangalore, India (Saha, A.; Ranmale, R.S.)
Abstract	SoC designs today comprise IP blocks from different design teams and vendors. Because of differing design styles being used on IPs, integrating them and verifying them is a challenge for design teams. One of the problems that we have found while integrating is the way reset or initialisation circuitry is implemented. Lack of knowledge of IPs often cause problems late in the design flow when we perform gate level simulations with backannotated delays, thus uncovering a bug due to either incorrect integration or incorrect assumed behaviour. Transition relation of registers can be modeled using binary decision diagrams (BDD). Using constant propagation techniques in formal verification the BDDs can be reduced to constant values. This paper describes how formal verification techniques are used in identifying uninitialized registers in SoC designs.
Starting Page	59
Ending Page	62
File Size	219602
Page Count	4
File Format	PDF
ISBN	0780374940
DOI	10.1109/ASIC.2002.1158031
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Circuit simulation Formal verification Boolean functions Registers Binary decision diagrams Logic design Silicon Instruments Delay
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Hybrid techniques for fast functional simulation

Formal verification of self-testing properties of combinational circuits

Improving structural FSM traversal by constraint-satisfying logic simulation

Binary decision diagrams and beyond: enabling technologies for formal verification

Formal verification using parametric representations of Boolean constraints

Implementing Symbolic Simulation Using SAT Solvers by Variables Partition

An enhanced cut-points algorithm in formal equivalence verification

Fast functional simulation using branching programs

Fast discrete function evaluation using decision diagrams

Using formal techniques for identifying uninitialized registers in SoC designs

Similar Documents

Hybrid techniques for fast functional simulation

Formal verification of self-testing properties of combinational circuits

Improving structural FSM traversal by constraint-satisfying logic simulation

Binary decision diagrams and beyond: enabling technologies for formal verification

Formal verification using parametric representations of Boolean constraints

Implementing Symbolic Simulation Using SAT Solvers by Variables Partition

An enhanced cut-points algorithm in formal equivalence verification

Fast functional simulation using branching programs

Fast discrete function evaluation using decision diagrams

Using formal techniques for identifying uninitialized registers in SoC designs