NDLI: A new low-power and area efficient RAKE receiver design without incurring performance degradation

Content Provider	IEEE Xplore Digital Library
Author	Hyung-Jin Lee Dong Sam Ha
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., USA (Hyung-Jin Lee; Dong Sam Ha)
Abstract	A new architecture for power and area efficient RAKE receivers for a third generation wireless WCDMA system is presented. The proposed approach based on parallel operations of code generators eliminates de-skew blocks of RAKE receivers and shares several blocks such that compensators, orthogonal variable spreading factor code generators and scrambling code generators are shared among all fingers, which leads to power and area reduction. When the proposed architecture is applied to a RAKE receiver with four fingers, it reduces power dissipation by 55.2% and the area by 38.1% without any system performance degradation.
Starting Page	251
Ending Page	255
File Size	269148
Page Count	5
File Format	PDF
ISBN	0780374940
DOI	10.1109/ASIC.2002.1158066
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fading Multipath channels Degradation Power generation Multiaccess communication Fingers Power dissipation Correlators Frequency Very large scale integration
Content Type	Text
Resource Type	Article

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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A new low-power and area efficient RAKE receiver design without incurring performance degradation