NDLI: A design methodology of vector unit for Emotion synthesis

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ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

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Design verification using formal techniques

Verifying sequential behavior with model checking

A semi-formal verification methodology

Research on floorplanning

Technology roadmap on SOC testing: issues on SOC testing in DSM era

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Studies on the layout algorithm for CGH in OEMCM systems design

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A frequency domain fast wavelet collocation method for high-speed circuit simulation

Using a hardware model checker to verify software

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Computer aided design of switched-current filters

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A modified data cache management scheme based on NTS structure

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Methods of improving rout ability in timing-driven placement

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CEP: a clock-driven ECO placement algorithm for standard-cell layout

A mixed mode placement algorithm for combined design of macro blocks and standard cells

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ASICosyn: co-synthesis of conditional task graphs with custom ASICs

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A design methodology of vector unit for Emotion synthesis

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2nd International Conference on ASIC

A design methodology of vector unit for Emotion synthesis

Content Provider	IEEE Xplore Digital Library
Author	Kamei, T.
Copyright Year	2001
Description	Author affiliation: Syst. LSI Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan (Kamei, T.)
Abstract	With advances in silicon technology and system integration technology, utmost care for RC-delay must be taken in high performance LSI design. This paper presents the design method applied to the vector unit (VU) implemented in PlayStation(R)-2 CPU, called the 'Emotion Engine'. This paper presents our design method which can estimate wire load by predicting wire shape, and the estimated RC delay is effectively used for pre-layout timing analysis. The method enables us to obtain accurate pre-layout timing result and reduce the design turn-around time. With this method, the VU has achieved an operating frequency of 300 MHz and 2.24 Giga floating operation per seconds (GFLOPS).
Sponsorship	Chinese Inst. Electron.
Starting Page	730
Ending Page	735
File Size	489278
Page Count	6
File Format	PDF
ISBN	0780366778
DOI	10.1109/ICASIC.2001.982667
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design methodology Delay estimation Wire Timing Silicon Large scale integration Engines Shape Delay effects Frequency
Content Type	Text
Resource Type	Article

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