NDLI: A novel configurable analog unit architecture

Content Provider	IEEE Xplore Digital Library
Author	Binlin Guo Feng Zhou Jiarong Tong
Copyright Year	2001
Description	Author affiliation: Microelectron. Dept., Fudan Univ., Shanghai, China (Binlin Guo)
Abstract	In this paper, a new architecture of configurable analog unit based on switch capacitor technology is presented. The architecture consists of four parts of input expansion, SC building block, self-calibrating OpAmp and clock control. The architecture not only achieves linear analog application such as integrator, gain amplifier, filter, etc., but also can be expediently configured to implementing some nonlinear analog applications. A programming mechanism using two programmable selector for parameter selector and function selector are illustrated for the architecture. The architecture is propitious to utilize configuration and technology mapping. As nonlinear analog application, a voltage control oscillator is implemented. Simulation result with HSPICE shows that for 0.6 /spl mu/ CMOS process, the relative error of voltage-frequency is less than 0.2%.
Sponsorship	Chinese Inst. Electron.
Starting Page	478
Ending Page	481
File Size	269367
Page Count	4
File Format	PDF
ISBN	0780366778
DOI	10.1109/ICASIC.2001.982604
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Field programmable analog arrays Switches CMOS technology Functional programming CMOS process Voltage Field programmable gate arrays Logic Capacitors
Content Type	Text
Resource Type	Article

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