NDLI: MPEG-2 TS generate system and its implementation with FPGA

Content Provider	IEEE Xplore Digital Library
Author	Dongliang Guan Songyu Yu Changtai Liang Xingdong Wang
Copyright Year	2001
Description	Author affiliation: Inst. of Image Commun. & Inf. Process., Shanghai Jiao Tong Univ., China (Dongliang Guan)
Abstract	In this paper, a MPEG-2 TS (transport stream) generation system is introduced. It can work as a TS generator source to provide a TS from hard disk in a cycling mode; it can also work as a TS recorder to receive a TS from a peripheral. A real-time PID filter, PID changing and bit rate changing are also realized in this system; Further the received TS can be analyzed and processed by a PC. In this paper, we briefly introduce the TS generate system's hardware architecture and working process. The system consists of a PCI interface card and a PC. The PCI interface card is implemented mainly with one FPGA (APEX 20K200 E). The system takes full advantage of the APEX20K's features of high integrity and flexibility that most functions are realized within one FPGA.
Sponsorship	Chinese Inst. Electron.
Starting Page	510
Ending Page	513
File Size	303226
Page Count	4
File Format	PDF
ISBN	0780366778
DOI	10.1109/ICASIC.2001.982612
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Bit rate Hardware Digital video broadcasting IEC standards ISO standards Hard disks Filters Electronics packaging Digital TV
Content Type	Text
Resource Type	Article

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