NDLI: Design Oriented Analysis of DC Link Current Observer of a Three-phase Double Conversion Uninterruptable Power System or Adjustable Speed Drive

Content Provider	IEEE Xplore Digital Library
Author	Lee, Kevin Wallace, Ian T. Bhadkamkar, Atul S.
Copyright Year	2007
Description	Author affiliation: Eaton Innovation Center, 4201 North 27th Street, Milwaukee, WI 53216. KevinLee@eaton.com (Lee, Kevin) \|\| Eaton Innovation Center, 4201 North 27th Street, Milwaukee, WI 53216. IanTWallace@eaton.com (Wallace, Ian T.) \|\| Eaton Innovation Center, 4201 North 27th Street, Milwaukee, WI 53216. AtulSBhadkamkar@eaton.com (Bhadkamkar, Atul S.)
Abstract	In this paper, a high performance dc link current observer is described and analyzed for a double conversion uninterruptible power system (UPS) or an adjustable speed drive (ASD). This second order observer identifies the dc link current drawn by the output inverter section. The observed load current is then used as a feedforward signal to input converter current regulator section for improving its dynamic response. The new contributions include the analysis on the system observability, observer sensitivity to system parameters, its command tracking performance, dc link voltage and load current dynamic disturbance rejection capabilities, all of which are not found in present literatures. In conjunction with the dc link current observer analysis, the current regulator bandwidth performance of the input ac-dc converter stage is characterized for both single and double update pulse width modulation (PWM) methods. The high performance resides in its fast dynamic response to the load power requirements resulting in dc link voltage variation, without using dc link current sensor or any communication channels. The solution is not only ideal for a stand alone UPS or ASD for low cost and high dynamic performance, but is particularly attractive for ac-dc converters suitable for common dc link systems. The analytical results are verified through the state-of-the-art simulation. All control algorithms are implemented in a Texas Instruments (TI) digital signal processor (DSP) and Xilinx field programmable gate array (FPGA) environment. The experimental setup of a 3- phase, 480V, 60Hz, 15 hp (11.
Starting Page	598
Ending Page	605
File Size	2907136
Page Count	8
File Format	PDF
ISBN	1424407133
ISSN	10482334
DOI	10.1109/APEX.2007.357576
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-02-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power system analysis computing Uninterruptible power systems Variable speed drives Performance analysis Pulse width modulation converters Regulators Voltage AC-DC power converters Pulse width modulation Field programmable gate arrays
Content Type	Text
Resource Type	Article

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