NDLI: Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization

Content Provider	IEEE Xplore Digital Library
Author	Kamal, M. Amiri, N.K. Kamran, A. Hoseini, S.A. Dehyadegari, M. Noori, H.
Copyright Year	2010
Description	Author affiliation: School of Electrical and Computer Engineering, University of Tehran (Kamal, M.; Amiri, N.K.; Kamran, A.; Hoseini, S.A.; Dehyadegari, M.; Noori, H.)
Abstract	Extending instruction set architecture (ISA) of embedded processors is an effective way to enhance performance and energy efficiency. The typical approaches for identifying custom instructions (CIs) limit the maximum number of input and output (I/O) operands to the available register file port. Recently, there are several work that explore CI candidates without imposing a limit on the number of input and output operands. In this paper, we present a new algorithm based on Particle Swarm Optimization (PSO) to identify CIs within a given data flow graph (DFG) and evaluate it for both categories of CI identification approaches (with and without I/O constrains). By novel evolving strategy, we enhance the quality of the results in our partitioning algorithm. Experimental results show that in most cases CI identification with I/O constraints based on PSO finds better or the same CIs in terms of performance compared to genetic algorithm (GA)[1] and ISEGEN [2] (96% and 90%, respectively). Comparing our proposed algorithm with [12] and [13] reveals that ours has a shorter run-time several order of magnitudes for large DFGs and is independent of the number of forbidden nodes. Moreover, we propose a modified version of PSO called Wrapper PSO that is up to 100× and 500× faster than GA and ISEGEN in large DFGs, respectively.
Starting Page	159
Ending Page	166
File Size	312755
Page Count	8
File Format	PDF
ISBN	9781424469666
ISSN	10636268
e-ISBN	9781424469673
e-ISBN	9781424469659
DOI	10.1109/ASAP.2010.5541012
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Particle swarm optimization Computational Intelligence Society Registers Energy efficiency Partitioning algorithms Genetic algorithms Acceleration Costs Computer aided instruction Embedded computing extensible processors custom instructions particle swarm optimization genetic algorithm
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors

Characterizing embedded applications for instruction-set extensible processors

Hardware Software Partitioning using Particle Swarm Optimization Technique

Efficient maximal convex custom instruction enumeration for extensible processors

CHIPS: Custom Hardware Instruction Processor Synthesis

Scalable custom instructions identification for instruction-set extensible processors

Disjoint Pattern Enumeration for Custom Instructions Identification

Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions

Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization

Similar Documents

Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor

An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors

Characterizing embedded applications for instruction-set extensible processors

Hardware Software Partitioning using Particle Swarm Optimization Technique

Efficient maximal convex custom instruction enumeration for extensible processors

CHIPS: Custom Hardware Instruction Processor Synthesis

Scalable custom instructions identification for instruction-set extensible processors

Disjoint Pattern Enumeration for Custom Instructions Identification

Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions

Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization