NDLI: A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications

Content Provider	IEEE Xplore Digital Library
Author	Bo Xiang Dan Bao Shuangqu Huang Xiaoyang Zeng
Copyright Year	2010
Description	Author affiliation: State Key Lab. of ASIC and System, Fudan University, Shanghai, China (Bo Xiang; Dan Bao; Shuangqu Huang; Xiaoyang Zeng)
Abstract	A fully-overlapped multi-mode QC-LDPC decoder architecture, adopting improved TDMP algorithm, is presented in this paper. With symmetrical four-stage pipelining, block column and row permutations, nonzero sub-matrix reordering, sum memory odd-even partition, and read-write bypass, two phases are fully overlapped and each phase scans nonzero sub-matrices one by one in block row-wise order without access conflicts to sum memories. The sum memories store not only variable node sums but also prior messages. In this case, it saves an additional FIFO of 13 440 bits. The decoder attains 248-287 Mb/s at 150 MHz and 15 iterations.
Starting Page	225
Ending Page	232
File Size	373229
Page Count	8
File Format	PDF
ISBN	9781424469666
ISSN	10636268
e-ISBN	9781424469673
e-ISBN	9781424469659
DOI	10.1109/ASAP.2010.5540958
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-07
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	WiMAX Iterative decoding Parity check codes Read-write memory Partitioning algorithms Sparse matrices Iterative algorithms Pipeline processing Throughput Application specific integrated circuits
Content Type	Text
Resource Type	Article

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