NDLI: An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 <formula formulatype=inline> <tex Notation=TeX>$mu$</tex></formula>m CMOS

Content Provider	IEEE Xplore Digital Library
Author	Bo Xiang Dan Bao Shuangqu Huang Xiaoyang Zeng
Copyright Year	1966
Abstract	This paper presents a partially-parallel dual-path fully-overlapped QC-LDPC decoder for the WiMAX system. By adopting five techniques including symmetrical six-stage pipelining, block column and row interleaving, nonzero sub-matrix reordering, sum memory quad-partition and read-write bypass, the decoder continuously scans nonzero sub-matrices two by two in the block row-wise order without any memory access conflict. Two phases are fully overlapped with each other, and the check node updating phase always takes the latest sums from the previous variable node updating phase. The sum memory stores not only the posterior sums but also the prior messages, which saves 11,520 memory bits. It only takes 48-54 clock cycles for the decoder to finish one iteration. The read-write accesses to sum memories are reduced by 24.3%-48.8%. Fabricated in the SMIC 0.13 μ m CMOS process, the decoder occupies 4.84 mm ² with core area of 3.03 mm², attains 847-955 Mb/s at 214 MHz and 10 iterations, and consumes 342-397 mW at 1.2 V with power efficiency of 39-46 pJ per bit per iteration.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1416
Ending Page	1432
Page Count	17
File Size	4202475
File Format	PDF
ISSN	00189200
Volume Number	46
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Clocks Program processors Iterative decoding WiMAX Pipeline processing Registers symmetrical six-stage pipelining Block column and row interleaving decoder architecture dual-path fully-overlapped nonzero sub-matrix reordering QC-LDPC codes read-write bypass
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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