NDLI: Reliability-aware co-synthesis for embedded systems

Content Provider	IEEE Xplore Digital Library
Author	Xie, Y. Li, L. Kandemir, M. Vijaykrishnan, N. Irwin, M.J.
Copyright Year	2004
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., Philadelphia, PA, USA (Xie, Y.; Li, L.; Kandemir, M.; Vijaykrishnan, N.; Irwin, M.J.)
Abstract	As technology scales, transient faults due to single event upsets have emerged as a key challenge for reliable embedded system design. This work proposes a design methodology that incorporates reliability into hardware-software co-design paradigm for embedded systems. We introduce an allocation and scheduling algorithm that efficiently handles conditional execution in multi-rate embedded systems, and selectively duplicates critical tasks to detect soft errors, such that the reliability of the system is increased. The increased reliability is achieved by utilizing the otherwise idle computation resources and incurs no resource or performance penalty. The proposed algorithm is fast and efficient, and is suitable for use in the inner loop of our hardware/software co-synthesis framework, where the scheduling routine has to be invoked many times.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on VLSI
Starting Page	41
Ending Page	50
File Size	452823
Page Count	10
File Format	PDF
ISBN	0769522262
ISSN	21600511
DOI	10.1109/ASAP.2004.1342457
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Embedded system Hardware Single event upset Costs Scheduling algorithm Aerospace electronics Computer architecture Signal processing algorithms Application software Time to market
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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