NDLI: COHRA: hardware-software co-synthesis of hierarchical distributed embedded system architectures

Content Provider	IEEE Xplore Digital Library
Author	Dave, B.P. Jha, N.K.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. Eng., Princeton Univ., NJ, USA (Dave, B.P.)
Abstract	Hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules such that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium-to-large scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the co-synthesis system, may itself be non-hierarchical or hierarchical. Traditional non-hierarchical architectures create communication and processing bottlenecks, and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives. In this paper, we address the problem of hardware-software co-synthesis of hierarchical distributed embedded system architectures from hierarchical or non-hierarchical task graphs. We show how our co-synthesis algorithm can be easily extended to consider fault tolerance or low power objectives or both. Although hierarchical architectures have been proposed before, to the best of our knowledge, this is the first time the notion of hierarchical task graphs and hierarchical architectures has been supported in a co-synthesis algorithm.
Starting Page	347
Ending Page	354
File Size	1198095
Page Count	8
File Format	PDF
ISBN	0818682248
ISSN	10639667
DOI	10.1109/ICVD.1998.646631
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-01-04
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Embedded system Computer architecture Real time systems Processor scheduling Scheduling algorithm Cost function Field programmable gate arrays Hardware Embedded software Pipeline processing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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