NDLI: Optimizing the memory bandwidth with loop morphing

Content Provider	IEEE Xplore Digital Library
Author	Gomez, J.I. Marchal, P. Verdoorlaege, S. Pinuel, L. Catthoor, L.
Copyright Year	2004
Description	Author affiliation: DACYA UCM, Madrid, Spain (Gomez, J.I.)
Abstract	The memory bandwidth largely determines the performance of embedded systems. However, very often compilers ignore the actual behavior of the memory architecture, causing large performance loss. To better utilize the memory bandwidth, several researchers have introduced instruction scheduling/data assignment techniques. Because they only optimize the bandwidth inside each basic block, they often fail to use all available bandwidth. Loop fusion is an interesting alternative to more globally optimize the memory access schedule. By fusing loops we increase the number of independent memory operations inside each basic block. The compiler can then better exploit the available bandwidth and increase the system's performance. However, existing fusion techniques can only combine loops with a conformable header. To overcome this limitation we present loop morphing; we combine fusion with strip mining and loop splitting. We also introduce a technique to steer loop morphing such that we find a compact memory access schedule. Experimental results show that with our approach we can decrease the execution time up to 88%.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on VLSI
Starting Page	213
Ending Page	223
File Size	437115
Page Count	11
File Format	PDF
ISBN	0769522262
ISSN	21600511
DOI	10.1109/ASAP.2004.1342472
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bandwidth Processor scheduling Strips Embedded system Memory architecture Performance loss Delay Runtime Costs Optimizing compilers
Content Type	Text
Resource Type	Article

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