NDLI: An optimal algo-tech-cuit for the knapsack problem

Content Provider	IEEE Xplore Digital Library
Author	Andonov, R. Rajopadhye, S.
Copyright Year	1993
Description	Author affiliation: IRISA, Rennes, France (Andonov, R.; Rajopadhye, S.)
Abstract	The authors first present a formal derivation and proof of correctness of a systolic array for the knapsack problem, an NP-complete problem whose dependency graph is not completely known statically. With q PEs, each with a fixed size memory, the arraystretch runs in /spl Gamma/(mc/q), which gives optimal speedup of the algorithm. However, it has an intricate tag-based control mechanism which is difficult to implement, and the authors improve the architecture so that the control can be implemented with two simple counters and a few flip-flops. Cofficient loading is done with a multi-rate clock which avoids the need for shadow registers. The authors then explore the tradeoff between the number of PEs and memory size, /spl alpha/, using the expected running time of the algorithm as a cost measure and a register level model of VLSI. It is shown analytically how /spl alpha/ may be chosen to optimize the total computation time, yielding an area time optimal circuit.<>
Starting Page	548
Ending Page	559
File Size	581875
Page Count	12
File Format	PDF
ISBN	0818634928
ISSN	10636862
DOI	10.1109/ASAP.1993.397174
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-25
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Systolic arrays NP-complete problem Counting circuits Flip-flops Clocks Costs Size measurement Time measurement Very large scale integration
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture

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