NDLI: Realization of a real time phasecorrelation chipset used in a hierarchical two step HDTV motion vector estimator

Content Provider	IEEE Xplore Digital Library
Author	Muller, K. Schirrmeister, F. Reventlow, C. Siebert, D. Reimers, J. Stoffers, C.
Copyright Year	1993
Description	Author affiliation: Institut fuer Mikroelektronik, TU-Berlin, Germany (Muller, K.; Schirrmeister, F.; Reventlow, C.; Siebert, D.; Reimers, J.; Stoffers, C.)
Abstract	The phasecorrelation algorithm - as a method for motion estimation - is a key component of todays TV and tomorrows HDTV-systems. One advantage of hardware realization of this algorithm for efficient real time processing - in opposite to blockmatching - is the possibility to process multiple pixels per system clock cycle. A suitable partition using three different VLSI-circuits to perform the phasecorrelation algorithm is going to be proposed. The system is able to handle block sizes from 32 /spl times/ 16 up to 128 /spl times/ 128, thus estimation of motion vectors limited to (-64..+64) pixel becomes possible. The estimated motion vectors are prepared by the phasecorrelation to be handled by a following blockmatching unit and are helpful to reduce hardware effort by limiting its search range. The combination of both algorithms leads to a two-step hierarchical motion estimator. To minimize the physical volume all external components except RAMs, have been integrated on three specialized chips, where all parameters are free programmable and no glue logic is required.<>
Starting Page	152
Ending Page	155
File Size	229431
Page Count	4
File Format	PDF
ISBN	0818634928
ISSN	10636862
DOI	10.1109/ASAP.1993.397133
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-25
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	HDTV Motion estimation Phase estimation Clocks Arithmetic TV Hardware Image coding Video compression Difference equations
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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