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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Benz, S.P. Burroughs, C.J. Hamilton, C.A. |
| Copyright Year | 2002 |
| Abstract | The authors have optimized the design and calculated the margins for a number of single flux quantum (SFQ) logic elements, including AND, OR, XOR, splitter, DC-to-SFQ converter, and SFQ-to-DC converter. These are the fundamental building blocks necessary to construct more complex logic functions such as the half adder and full adder. Experimental tests of the primary gates, the AND, OR, XOR, and splitter, tests were made by imbedding each test gate between DC-to-SFQ converters at the inputs and SFQ-to-DC converters at the outputs. Automated testing of each circuit was used to determine functionality, optimum bias levels, and margins. The experimental bias current margins for each gate are consistent with the simulations.< |
| Sponsorship | Council on Superconductivity Appl. Superconductivity Conference Inc MIT |
| Starting Page | 2582 |
| Ending Page | 2585 |
| Page Count | 4 |
| File Size | 573335 |
| File Format | |
| ISSN | 10518223 |
| Volume Number | 3 |
| Issue Number | 1 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1993-03-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit testing Josephson junctions Adders SQUIDs Design optimization Logic gates Voltage DC-DC power converters NIST Logic design |
| Content Type | Text |
| Resource Type | Article |
| Subject | Condensed Matter Physics Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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