NDLI: Josephson logic and memory circuits

Content Provider	IEEE Xplore Digital Library
Author	Herrell, D.
Copyright Year	1965
Abstract	Josephson logic and memory circuits have rapidly developed over the last few years. Initial exploratory circuits and devices, designed with linewidths of the order of 25μm were soon developed down to linewidths in the 5 to 2.5μm range with perhaps the most significant modification being the change from in-line gates to interferometer devices (SQUIDS) with higher sensitivity, lower capacitance and higher speed. Present devices at a 2.5μm linewidth offer LSI logic chips with typical delays of the order of 30 ps per gate at a total chip dissipation level of 6 mW, including the power supply. NDRO RAM chips with densities of 4K bits/chip are possible for high-speed cache memory with a 2.5μm linewidth technology and an access time of the order of 0.5 ns. For main memory, on the other hand, a 2.5μm minimum linewidth technology is expected to yield approximately 16K bits/chip of DRO RAM with an access time estimated at 15 ns at a dissipation level of only 40 μW/chip.
Sponsorship	IEEE Magnetics Society
Starting Page	1880
Ending Page	1885
Page Count	6
File Size	1129117
File Format	PDF
ISSN	00189464
Volume Number	15
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1979-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Josephson junctions Circuits Read-write memory SQUIDs Capacitance Large scale integration Logic devices Delay Power supplies Cache memory
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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