NDLI: 2µm - bubble device optimization

Content Provider	IEEE Xplore Digital Library
Author	Gergis, I. Tocci, L. Lee, W. Heinz, D.
Copyright Year	1965
Abstract	We report on the improvement in 8-9μm period devices as compared to simple scaling of the present state-of-the-art 16μm period devices. Optimizations of garnet, and processing parameters and device component design were made to reduce the chip drive (field, voltage). We found that the using larger bubble size than the scaled down value (2.2μm instead of 1.7μm) is most effective in reducing the drive field and improving gap tolerance. Conductor and permalloy thickness were kept at 3500Å (scaled down value is ≈2000Å). The spacer thickness, however, was close to the scaled down value of 4000 to 4500Å to improve the stretcher upper bias margin. Although non-planar devices sometimes showed very good margins at low drive fields (10% at 50 Oe drive), it is felt that planar processing is necessary to maintain reproducibility. Device component design based on extra large permalloy element such as double period major loops and 3π-corner in the replicator switch were found to have good overall bias margins of 26 Oe at 45 to 55 Oe drives. Operation at 150 kHz with 55 Oe drive showed as bias margin of 10% or more in the temperature range of -25 to 80°C. At 250 kHz an increase of 5 Oe in the minimum drive field was observed.
Sponsorship	IEEE Magnetics Society
Starting Page	1718
Ending Page	1718
Page Count	1
File Size	66190
File Format	PDF
ISSN	00189464
Volume Number	15
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1979-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stochastic processes Testing Temperature distribution Physics White noise Random processes Magnetic devices Reliability theory Degradation Crystalline materials
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Theoretical analysis of longevity testing on bubble memory devices

Theoretical analysis of longevity testing on bubble memory devices

Characteristics of packaged 256 kbit enhanced density 3 µm bubble devices with improved performance

Margin degradation in the long-term testing of 3 µm bubble devices

New ion-implantation method for 4-µm period bubble device

Design of 2 µm-period minor loops in hybrid bubble memory devices

68 kbit capacity 16 µm-period magnetic bubble memory chip design with 2 µm minimum features

Optimization of minor loop propagation for 8 µm period bubble memory devices

High Curie temperature vanadium containing films for 8µm period magnetic bubble devices

2µm - bubble device optimization

Similar Documents

Theoretical analysis of longevity testing on bubble memory devices

Theoretical analysis of longevity testing on bubble memory devices

Characteristics of packaged 256 kbit enhanced density 3 &#181;m bubble devices with improved performance

Margin degradation in the long-term testing of 3 &#181;m bubble devices

New ion-implantation method for 4-&#181;m period bubble device

Design of 2 &#181;m-period minor loops in hybrid bubble memory devices

68 kbit capacity 16 &#181;m-period magnetic bubble memory chip design with 2 &#181;m minimum features

Optimization of minor loop propagation for 8 &#181;m period bubble memory devices

High Curie temperature vanadium containing films for 8&#181;m period magnetic bubble devices

2&#181;m - bubble device optimization

Characteristics of packaged 256 kbit enhanced density 3 µm bubble devices with improved performance

Margin degradation in the long-term testing of 3 µm bubble devices

New ion-implantation method for 4-µm period bubble device

Design of 2 µm-period minor loops in hybrid bubble memory devices

68 kbit capacity 16 µm-period magnetic bubble memory chip design with 2 µm minimum features

Optimization of minor loop propagation for 8 µm period bubble memory devices

High Curie temperature vanadium containing films for 8µm period magnetic bubble devices

2µm - bubble device optimization