NDLI: A micro-processor interfaced 1 MBIT bubble memory

Content Provider	IEEE Xplore Digital Library
Author	Yoshizawa, S. Sugie, M. Kita, Y. Yamaguchi, N. Mayama, K. Asano, A. Nishida, H. Ishida, F. Sugita, Y. Kurokawa, S.
Copyright Year	1965
Abstract	Compact solid-state read-write memories with non-volatility are much desired for micro-processor applications. 1) Recently, we have realized a very compact and convenient 1Mbit bubble memory board, using newly developed controller LSI (BMC: Bubble Memory Controller) and high density 256 kbit bubble memory chips (8μ period). The memory board is only 18cm × 15cm size and activated by a single power source of +5V. An outstanding feature of this memory is a perfect protection of memory contents against power supply accidents (+5V, open or short) . This protection is realized using a new method by BMC and a peripheral circuit on the board. Another feature is a new automatic handling of defect loops in the bubble memory chips. A defect loop map is stored in the special page address of bubble chip itself and BMC reads this map and stores it into an internal RAM of BMC, when power switch is turned on. Using this information, BMC masks the defect loop automatically. The compactness of this board originates from the realization of BMC-LSI ( n-Mos ) . BMC contains about 15k transistors and controls the bubble chip using the data of 6 kbit internal ROM. Present memory can be connected directly to bus lines of micro-processor 6800 series and 8080 series. A 256 kbit bubble chip employs a block-replicator and even-odd organization and is composed of 280 minor loops with 1135 positions. Its high density (8μ period) was achieved by the introduction of a new planer process using PIQ resins. The performances of this memory board will be described.
Sponsorship	IEEE Magnetics Society
Starting Page	1904
Ending Page	1904
Page Count	1
File Size	77073
File Format	PDF
ISSN	00189464
Volume Number	15
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1979-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Read-write memory Protection Solid state circuits Large scale integration Power supplies Accidents Random access memory Automatic control Read only memory Metalworking machines
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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