NDLI: Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption

Content Provider	IEEE Xplore Digital Library
Author	Ingelsson, U. Goel, S.K. Larsson, E. Marinissen, E.J.
Copyright Year	1968
Abstract	System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time, for which the abortable test unit can be a module test, a test pattern or a clock cycle. Given an SOC, with test architecture consisting of module test wrappers and test access mechanisms (TAMs), and given module test pass probabilities, we schedule the tests on each TAM to minimize the expected test time. We describe four scheduling heuristics, one without and three with preemption. Experimental results for the ITC'02 SOC Test Benchmarks show 3.5 and 20 percent reduction of expected test time in SOCs with 0.89 and 0.71 SOC test pass probability respectively, without modification of SOC or ATE. Further experiments show how accurate estimates for the module test pass probability or the distribution of pass probability over test patterns need to be to lead to effective test scheduling.
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	3335
Ending Page	3347
Page Count	13
File Size	858280
File Format	PDF
ISSN	00189340
Volume Number	64
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-chip Integrated circuits Manufacturing processes Job shop scheduling Three dimensional displays Failure analysis preemptive scheduling System-on-Chip stacked integrated circuit manufacturing test modular test reject-oriented analysis abort-onfail test scheduling abort-on-fail
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

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