NDLI: <inline-formula><tex-math>$2^n$</tex-math><alternatives> <inline-graphic xlink:type=simple xlink:href=sousa-ieq1-2401026.gif/></alternatives></inline-formula> RNS Scalers for Extended 4-Moduli Sets

Content Provider	IEEE Xplore Digital Library
Author	Sousa, L.
Copyright Year	1968
Abstract	Scaling is a key important arithmetic operation and is difficult to perform in Residue Number Systems (RNS). This paper proposes a comprehensive approach for designing efficient and accurate 2ⁿ RNS scalers for important classes of moduli sets that have large dynamic ranges. These classes include the traditional 3-moduli set, but the exponent of the power of two modulo is augmented by a variable value x ({2ⁿ - 1; 2^n+x, 2ⁿ + 1}), and any extended set with an additional modulo m₄ ({2ⁿ - 1, 2^n+x, 2ⁿ + 1[, m⁴]}). The proposed approach embeds scaling into the formulation of the Chinese remainder theorem and the mixed radix system, and it exploits the properties of the target moduli sets to perform scaling explicitly in the RNS domain. This is accomplished by operating hierarchically on each channel without requiring reverse and forward conversions. Simple memoryless VLSI architectures are proposed based on the obtained formulations. The relative assessment indicates that not only are these architectures comprehensive and suitable for configurable systems, but they are also more efficient than the related state of the art in terms of both performance and energy. The experimental results obtained for a 90 nm CMOS ASIC technology show improvements in the area-delay product, normalized with respect to the dynamic range, of up to 57 and 146 percent with the proposed scalers for the augmented 3-moduli set (dynamic range of 4n - 1 bits) and an extended 4-moduli set (dynamic range of 6n bits), respectively. These improvements increase to 64:9 and 263 percent when the energy required per scaling is measured. The proposed scalers are not only flexible and cost-effective, but they are also suitable for designing and implementing energy-constrained devices, particularly mobile systems.
Sponsorship	IEEE Computer Society Technical Committee on Distributed Process IEEE Computer Society Technical Committee on VLSI IEEE Technical Committee on Computer Architecture IEEE Computer Society
Starting Page	3322
Ending Page	3334
Page Count	13
File Size	1617907
File Format	PDF
ISSN	00189340
Volume Number	64
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Dynamic range Very large scale integration Computer architecture Random access memory Complexity theory Algorithm design and analysis FPGA Residue number system scaling Chinese remainder theorem VLSI architecture ASIC
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Software Hardware and Architecture

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Fast and Flexible Architectures for RNS Arithmetic Decoding

$2^n$ RNS Scalers for Extended 4-Moduli Sets

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