NDLI: A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Jiao Cheng Nan Qi Chiang, P.Y. Natarajan, A.
Copyright Year	1966
Abstract	A PSK receiver (RX) is proposed that employs a digital-intensive architecture based on sub-sampling, Q-enhancement, and digital IF to enable low-power (1.3 mW) and low-voltage (0.6 V) operation. Implemented in 65 nm CMOS, this work is compatible with the IEEE 802.15.6 (WBAN) narrowband physical layer specification and achieves -91 dBm and -96 dBm sensitivity at 10^-3 BER for π/4-DQPSK and π/2-DBPSK modulation respectively. The proposed highly digital architecture and supply voltage scaling lead to a 3x improvement in RX energy efficiency and minimize silicon area consumption (~ 0.35 mm² in 65 nm CMOS) while achieving state-of-the-art sensitivity. While this implementation focuses on WBAN demodulation, the proposed architecture and circuit techniques are generally applicable to RX targeting ultra-low power consumption for sensor networks.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	3018
Ending Page	3030
Page Count	13
File Size	2822101
File Format	PDF
ISSN	00189200
Volume Number	49
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise Radio frequency Gain Power demand CMOS integrated circuits Tuning Standards WBAN $\pi/2$-DBPSK $\pi/4$-DQPSK CMOS digital IF digital RF low power low voltage narrowband PSK ${\rm Q}$-enhancement receiver (RX) sub-sampling
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

0.6-V 2.1-mW RF receiver based on passive mixing and master–slave common-mode rejection technique in 65 nm CMOS

8.1 nJ/b 2.4 GHz Short-Range Communication Receiver in 65 nm CMOS

A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS

Low-power 850 nm optoelectronic integrated circuit receiver fabricated in 65 nm complementary metal–oxide semiconductor technology

Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

Analysis of wide-IF-band 65 nm-CMOS mixer for 77–110 GHz radio-astronomical receiver design

Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS

0.36 V PGA combining single-stage OTA and input negative transconductor for low energy RF receivers

A Practical Design of X-Band Receiver Front-End in 65-nm CMOS

A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS

Similar Documents

0.6-V 2.1-mW RF receiver based on passive mixing and master–slave common-mode rejection technique in 65 nm CMOS

8.1 nJ/b 2.4 GHz Short-Range Communication Receiver in 65 nm CMOS

A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS

Low-power 850 nm optoelectronic integrated circuit receiver fabricated in 65 nm complementary metal–oxide semiconductor technology

Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

Analysis of wide-IF-band 65 nm-CMOS mixer for 77–110 GHz radio-astronomical receiver design

Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS

0.36 V PGA combining single-stage OTA and input negative transconductor for low energy RF receivers

A Practical Design of X-Band Receiver Front-End in 65-nm CMOS

A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS