NDLI: A 780 mW 4 <formula formulatype=inline><tex Notation=TeX>$times$</tex> </formula> 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Singh, U. Garg, A. Raghavan, B. Huang, N. Heng Zhang Zhi Huang Momtaz, A. Jun Cao
Copyright Year	1966
Abstract	This paper describes a reconfigurable 4 × 28 Gb/s transceiver supporting 100 GbE/40 GbE standards. In each lane, the transmitter incorporates a 3-tap FIR with independent output phase adjustment, and the receiver has a half-rate CDR with a dedicated eye-monitor channel. There is a global resonant clock distribution network implemented using programmable distributed on-chip inductors. Implemented in a 40 nm CMOS process, the TX output measures 1.87 pspp DJ and 202 fsrms RJ. The RX jitter tolerance is 0.46 UIpp at 80 MHz with an input sensitivity of 27 mVpp-diff. The transceiver achieves BER on a channel with 20 dB loss at Nyquist, dissipating only 780 mW from a 0.9 V supply for all four lanes at 28 Gb/s operation.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	3116
Ending Page	3129
Page Count	14
File Size	3284181
File Format	PDF
ISSN	00189200
Volume Number	49
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Bandwidth Transceivers Power demand Receivers Inductors Standards VSR Calibrated resistor CFP2 dual VCO folded active inductor gearbox half-rate CDR intersymbol interference (ISI) jitter tolerance low power multiplexer 100-Gigabit Ethernet programmable clock driver transceiver
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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