NDLI: A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Musah, T. Jaussi, J. Balamurugan, G. Hyvonen, S. Hsueh, T.-C. Keskin, G. Shekhar, S. Kennedy, J. Sen, S. Inti, R. Mansuri, M. Leddige, M. Horine, B. Roberts, C. Mooney, R. Casper, B.
Copyright Year	1966
Abstract	This paper details the design of an 8-lane bidirectional link for both within-the-box and external communications in 22 nm CMOS technology. A low profile connector with a high density cable assembly ensure a data rate of up to 32 Gb/s per lane while maintaining channel loss below 25 dB. Channel equalization is performed by a combination of a 3-tap feed-forward equalizer (FFE), single-stage continuous-time linear equalizer (CTLE) and a 6-tap decision-feedback equalizer (DFE). Collaborative timing recovery is used to enable lane characterization without degrading jitter performance. Phase error decimation, with a conditional phase detection scheme, is used to reduce the DFE complexity by 50%. Power consumption over a wide range of data rates from 4 to 32 Gb/s is reduced by using regulated CMOS clocking with lane bundling, low swing transmitter with a source-series terminated (SST) driver and a highly reconfigurable receiver with an active inductor CTLE. At a lane data rate of 32 Gb/s, over a 0.5 m cable with 16 dB of loss, a transceiver lane consumes 205 mW from a 1.07 V supply. The power scales down to 26 mW from a 0.72 V supply at 8 Gb/s, when transmitting over a channel with 8 dB loss. The active silicon area per lane is 0.079 mm².
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	3079
Ending Page	3090
Page Count	12
File Size	2851834
File Format	PDF
ISSN	00189200
Volume Number	49
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Decision feedback equalizers Phase detection Collaboration CMOS integrated circuits Timing Receivers source-series terminated (SST) driver Active inductor CTLE bidirectional link collaborative CDR conditional phase detection decision-feedback equalizer (DFE) phase error decimation regulated CMOS clocking
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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