NDLI: New Flash ADC Scheme With Maximal 13 Bit Variable Resolution and Reduced Clipped Noise for High-Performance Imaging Sensor

Content Provider	IEEE Xplore Digital Library
Author	Xiangliang Jin Zhibi Liu Jun Yang
Copyright Year	2001
Abstract	This paper presents a high-performance complementary metal-oxide-semiconductor (CMOS) imager with a new analog-to-digital-converter (ADC) scheme. The new ADC scheme, adopting the visual perception of human eyes, has realized a maximal 13 bit variable resolution and reduced clipped noise for imaging. The response probability of human eyes to a flashlight falls in the region of [-1+σ, 1-σ] of a normal distribution, where σ is the standard deviation. In the region effective to human eyes [-1+σ, 1-σ], there exists a point corresponding to a maximum 13 bit variable resolution to improve the image quality and to save the power consumption and the chip size of sensors. The new ADC architecture uses an adjustable reference at both the top and bottom of the series of nonuniform resistors to reduce the clipped noise and to provide a wide dynamic range to image sensors. Based on reports of similar device design in the literature, this paper is particularly related to achieving a higher performance without increasing the chip size and power consumption. UXGA CMOS sensors with the newly developed ADC scheme are fabricated by the 0.18-μm CMOS process. The test results show improved image quality compared to typical CMOS products with a linear ADC. Test results also show 79-dB signal-to-noise ratio (at gain=0 dB) with a power consumption of 90 mW at 54 MHz.
Sponsorship	IEEE Sensors Council
Starting Page	167
Ending Page	171
Page Count	5
File Size	532926
File Format	PDF
ISSN	1530437X
Volume Number	13
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Visual perception Analog-digital conversion Dynamic range Resistors CMOS image sensors variable resolution Analog to digital converter (ADC) clipped noise complementary metal-oxide-semiconductor (CMOS) image sensor dynamic range (DR)
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Wide-Dynamic-Range CMOS Image Sensor Based on Multiple Short Exposure-Time Readout With Multiple-Resolution Column-Parallel ADC

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC

An Enhanced Dynamic-Range CMOS Image Sensor Using a Digital Logarithmic Single-Slope ADC

A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme

A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications

An Ultra Low Power Encoder for 5 Bit Flash ADC

84-dB Range Logarithmic Digital-to-Analog Converter in CMOS 0.18- $muhbox{m}$ Technology

An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

A Low Noise Wide Dynamic Range CMOS Image Sensor With Low-Noise Transistors and 17b Column-Parallel ADCs

New Flash ADC Scheme With Maximal 13 Bit Variable Resolution and Reduced Clipped Noise for High-Performance Imaging Sensor

Similar Documents

A Wide-Dynamic-Range CMOS Image Sensor Based on Multiple Short Exposure-Time Readout With Multiple-Resolution Column-Parallel ADC

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC

An Enhanced Dynamic-Range CMOS Image Sensor Using a Digital Logarithmic Single-Slope ADC

A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme

A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications

An Ultra Low Power Encoder for 5 Bit Flash ADC

84-dB Range Logarithmic Digital-to-Analog Converter in CMOS 0.18- $muhbox{m}$ Technology

An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

A Low Noise Wide Dynamic Range CMOS Image Sensor With Low-Noise Transistors and 17b Column-Parallel ADCs

New Flash ADC Scheme With Maximal 13 Bit Variable Resolution and Reduced Clipped Noise for High-Performance Imaging Sensor