NDLI: Monolithic Pixel Sensors for Fast Silicon Vertex Trackers in a Quadruple Well CMOS Technology

Content Provider	IEEE Xplore Digital Library
Author	Zucca, S. Gaioni, L. Ratti, L. Re, V. Traversi, G. Bettarini, S. Forti, F. Morsani, F. Rizzo, G. Bosisio, L. Rashevskaya, I.
Copyright Year	1963
Abstract	Apsel4well is a monolithic active pixel sensor (MAPS) chip intended for application to fast and low material silicon vertex trackers for future experiments at high intensity machines. The design is based on a 180 nm CMOS process with quadruple well option called INMAPS. This technology makes it possible to increase the in-pixel intelligence as compared to standard three transistor MAPS and their variants. Moreover, the availability of a high resistivity epitaxial layer is confirmed to lead to further improvements in terms of charge collection performance and radiation resistance. This paper, after providing some details on the INMAPS process, focuses on the analog front-end section of the pixel readout chain. Measurement results on the main analog channel parameters, like charge sensitivity and equivalent noise charge, are given along with charge collection properties evaluation through ⁹⁰Sr/ ⁹⁰Y spectrum measurements and laser stimulation. Characterization data were also used for validating a TCAD model of the device. Finally, selected results from a neutron irradiation campaign with fluences up to 2.7 × 10¹³ 1 MeV neutron equivalent/cm ² will be shown.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	2343
Ending Page	2351
Page Count	9
File Size	1173315
File Format	PDF
ISSN	00189499
Volume Number	60
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Epitaxial layers Conductivity Standards Sensitivity Noise Capacitance Charge measurement quadruple well process CMOS MAPS low noise design particle tracking
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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