NDLI: Fast Power- and Slew-Aware Gated Clock Tree Synthesis

Content Provider	IEEE Xplore Digital Library
Author	Jingwei Lu Wing-Kai Chow Chiu-Wing Sham
Copyright Year	1993
Abstract	Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is an effective approach to reduce the dynamic power usage. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power- and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on Elmore RC model. In PACTS, the topology of the clock tree is constructed with simultaneous buffer/gate insertion, which reduces the switched capacitance. In PSACTS, a more practical clock slew constraint is applied. Compared to previous works, clock tree synthesis is done first and followed by the insertions of clock gates. The clock slew changes a lot after the insertions of clock gates in real cases. In our work, the clock tree is constructed simultaneously with the insertions of clock gates. This ensures the limitation of the clock slew can be strictly satisfied while the limitation of the clock slew is always applied in the real design. The experimental results show that the power cost of our work is smaller and the runtime is reduced. The slew rate constraint is satisfied with a small clock skew from SPICE estimation. Generally, our work has better performance, improved efficiency and is more practical to be applied in the industry.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	2094
Ending Page	2103
Page Count	10
File Size	1413040
File Format	PDF
ISSN	10638210
Volume Number	20
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Logic gates Capacitance Power demand Topology Design automation Integrated circuit modeling design automation Clock gating clock tree synthesis
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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